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november 2006 rev 5 1/35 1 m29f010b 1 mbit (128kb x8, uniform block) single supply flash memory feature summary single 5v10% supply voltage for program, erase and read operations access time: 45 ns programming time ? 8 s per byte typical 8 uniform 16 kbytes memory blocks program/erase controller ? embedded byte program algorithm ? embedded multi-block/chip erase algorithm ? status register polling and toggle bits erase suspend and resume modes ? read and program another block during erase suspend unlock bypass program command ? faster production/batch programming low power consumption ? standby and automatic standby 100,000 program/erase cycles per block 20 years data retention defectivity below 1 ppm/year electronic signature ? manufacturer code: 20h ? device code: 20h ecopack ? packages available tsop32 (n) 8 x 20mm plcc32 (k) www.st.com
contents m29f010b 2/35 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 address inputs (a0-a16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 data inputs/outputs (dq0-dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 vss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8 block protection and blocks unprotection . . . . . . . . . . . . . . . . . . . . . . . . 12 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 read/reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 auto select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 unlock bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 unlock bypass program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 unlock bypass reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 chip erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.10 erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
m29f010b contents 3/35 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 data polling bit (dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 toggle bit (dq6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 error bit (dq5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 erase timer bit (dq3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 alternative toggle bit (dq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
list of tables m29f010b 4/35 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. uniform block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. program erase times and program erase endurance cycles. . . . . . . . . . . . . . . . . . . . . . . 19 table 6. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. plcc32 ? 32 lead plastic leaded chip carrier, package mechanical data. . . . . . . . . . . . 31 table 15. tsop32 ? 32 lead plastic thin small outline, 8 x 20mm, package mechanical data . . . . 32 table 16. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
m29f010b list of figures 5/35 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. plcc connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5. data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6. ac testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11. plcc32 ? 32 lead plastic leaded chip carrier, package outline . . . . . . . . . . . . . . . . . . . 31 figure 12. tsop32 ? 32 lead plastic thin small outline, 8 x 20mm, package outline . . . . . . . . . . . . 32
summary description m29f010b 6/35 1 summary description the m29f010b is a 1 mbit (128kb x8) non-volatile memory that can be read, erased and reprogrammed. these operations can be performed using a single 5v supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. each block can be protected independently to prevent accidental program or erase commands from modifying the memory. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to cont rol the memory is consistent with jedec standards. chip enable, output enable and write enable signals control the bus operation of the memory. they allow simple connection to most microprocessors, often without additional logic. the memory is offered in plcc32, tsop32 (8 x 20mm) packages and it is supplied with all the bits erased (set to ?1?). in order to meet environmental requirements, st offers the m29f010b in ecopack ? packages. ecopack packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
m29f010b summary description 7/35 figure 1. logic diagram table 1. signal names a0-a16 address inputs dq0-dq7 data inputs/outputs e chip enable g output enable w write enable v cc supply voltage v ss ground nci not connected internally ai02735 17 a0-a16 w dq0-dq7 v cc m29f010b e v ss 8 g
summary description m29f010b 8/35 figure 2. plcc connections figure 3. tsop connections ai02737 nc a13 a10 dq5 17 a1 a0 dq0 dq1 dq2 dq3 dq4 a7 a4 a3 a2 a6 a5 9 w a8 1 a16 a9 dq7 a12 a14 32 nc v cc m29f010b a15 a11 dq6 g e 25 v ss a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a14 a11 g e dq5 dq1 dq2 dq3 dq4 dq6 nc w a16 a12 nc v cc a15 ai02738 m29f010b 8 1 9 16 17 24 25 32 v ss
m29f010b summary description 9/35 m table 2. uniform block addresses # size (kbytes) address range 7 16 1c000h-1ffffh 6 16 18000h-1bfffh 5 16 14000h-17fffh 4 16 10000h-13fffh 3 16 0c000h-0ffffh 2 16 08000h-0bfffh 1 16 04000h-07fffh 0 16 00000h-03fffh
signal descriptions m29f010b 10/35 2 signal descriptions see figure 1: logic diagram and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a16) the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the internal state machine. 2.2 data inputs/outputs (dq0-dq7) the data inputs/outputs output the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state machine. 2.3 chip enable (e ) the chip enable, e , activates the memory, allowing bus read and bus write operations to be performed. when chip enable is high, v ih , all other pins are ignored. 2.4 output enable (g ) the output enable, g , controls the bus read operation of the memory. 2.5 write enable (w ) the write enable, w , controls the bus write operation of the memory?s command interface. 2.6 v cc supply voltage the v cc supply voltage supplies the power for all operations (read, program, erase etc.). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from accidentally damaging the data during power up, power down and power surges. if the program/erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc4 .
m29f010b bus operations 11/35 2.7 vss ground the v ss ground is the reference for all voltage measurements. 3 bus operations there are five standard bus operations that control the device. these are bus read, bus write, output disable, standby and automatic standby. see table 3: bus operations , for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. 3.1 bus read bus read operations read from the memory cells, or specific registers in the command interface. a valid bus read operation involves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs /outputs will output the value, see figure 8: read mode ac waveforms and table 11: read ac characteristics , for details of when the output becomes valid. 3.2 bus write bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the address inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. output enable must remain high, v ih , during the whole bus write operation. see figure 9: write ac waveforms, write enable controlled , figure 10: write ac waveforms, chip enable controlled , table 12: write ac characteristics, write enable controlled and table 13: write ac characteristics, chip enable controlled , for details of the timing requirements. 3.3 output disable the data inputs/outputs are in the high impedance state when output enable is high, v ih .
bus operations m29f010b 12/35 3.4 standby when chip enable is high, v ih , the data inputs/outputs pins are placed in the high- impedance state and the supply current is reduced to the standby level. when chip enable is at v ih the supply current is reduced to the ttl standby supply current i cc2 . to further reduce the supply current to the cmos standby supply current, i cc3 , chip enable should be held within v cc 0.2v. for standby current levels see table 10: dc characteristics . during program or erase oper ations the memory will contin ue to use the program/erase supply current, i cc4 , for program or erase operations until the operation completes. 3.5 automatic standby if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 150ns or more the memory enters automatic standby where the internal supply current is reduced to the cmos standby supply current, i cc3 . the data inputs/outputs will still output data if a bus read operation is in progress. 3.6 special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus operations are intended for use by programming equipment and are not usually used in applications. they require v id to be applied to some pins. 3.7 electronic signature the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in ta b l e 3 : bus operations . 3.8 block protection and blocks unprotection each block can be separately protected against accidental program or erase. protected blocks can be unprotected to allow data to be changed. block protection and blocks unprotection operations must only be performed on programming equipment. for further information refer to application note an1122, applying protection and unprotection to m29 series flash memory.
m29f010b bus operations 13/35 table 3. bus operations (1) 1. x = v il or v ih . operation e g w address inputs data inputs/outputs bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih xhi-z standby v ih xxx hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih 20h read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih 20h
command interface m29f010b 14/35 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. failure to observe a valid sequence of bus write operations will resu lt in the memory retu rning to read mode. the long command sequences are imposed to maximize data security. the commands are summarized in table 4: commands . refer to ta b l e 4 in conjunction with the text descriptions below. 4.1 read/reset command the read/reset command returns the memory to its read mode where it behaves like a rom or eprom. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. if the read/reset command is issued during a block erase operation or following a programming or erase error th en the memory will take upto 10 s to abort. during the abort period no valid data can be read from the memory. issuing a read/reset command during a block erase operation will leave invalid data in the memory. 4.2 auto select command the auto select command is used to read the manufacturer code, the device code and the block protection status. three consecutive bu s write operations are required to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until another command is issued. from the auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the manufacturer code for stmicroelectronics is 20h. the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . the device code for the m29f010b is 20h. the block protection status of each block can be read using a bus read operation with a0 = v il , a1 = v ih , and a14-a16 specifying the address of the block. the other address bits may be set to either v il or v ih . if the addressed block is protected then 01h is output on the data inputs/outputs, otherwise 00h is output.
m29f010b command interface 15/35 4.3 program command the program command can be used to program a value to one address in the memory array at a time. the command requires four bus write operations, the final write operation latches the address and data in the internal state machine and starts the program/erase controller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is ne ver read and no error condition is given. during the program operation the memory will i gnore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 5: program erase times and program erase endurance cycles . bus read operations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operat ion has completed the memory will re turn to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. note that the program command cannot change a bit set at ?0? back to ?1?. one of the erase commands must be used to set all the bits in a block or in the whole me mory from ?0? to ?1?. 4.4 unlock bypass command the unlock bypass command is used in conjunction with the unlock bypass program command to program the memory. when the access time to the device is long (as with some eprom programmers) considerable time saving can be made by using these commands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been is sued the memory will only accept the unlock bypass program command and the unlock bypass reset command. the memory can be read as if in read mode. 4.5 unlock bypass program command the unlock bypass program command can be used to program one address in memory at a time. the command requires two bus write operations, the final write operation latches the address and data in the internal state machine and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the program operation using the program command. a protected block cannot be programmed; the operation cannot be aborted and the status register is read. errors must be reset using the read/reset command, which leaves the device in unlock bypass mode. see the program command for details on the behavior. 4.6 unlock bypass reset command the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command.
command interface m29f010b 16/35 4.7 chip erase command the chip erase command can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation appears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands. it is not possible to issue any command to abort the operation. typical chip erase times are given in ta bl e 5 : p r o g r a m erase times and program erase endurance cycles . all bus read operations during the chip erase operation will output the st atus register on the data in puts/outputs. see the section on the status register for more details. after the chip erase operation has complet ed the memory will return to the read mode, unless an error has occurred. when an error oc curs the memory will co ntinue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the chip erase command sets all of the bits in unprotected blocks of the memory to ?1?. all previous data is lost. 4.8 block erase command the block erase command can be used to erase a list of one or more blocks. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50s of the last block. the 50s timer restarts when an additional block is selected. the status register can be read after the sixth bus write operation. see the status register for details on how to identify if the program/erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate wit hin about 100s, leaving the data un changed. no erro r condition is given when protected blocks are ignored. during the block erase operat ion the memory will ignore a ll commands except the erase suspend and read/reset commands. typical block erase times are given in ta bl e 5 : program erase times and program erase endurance cycles . all bus read operations during the block erase operation will output the status register on t he data inputs/outputs. see the section on the status register for more details. after the block erase operation has complete d the memory will return to the read mode, unless an error has occurred. when an error oc curs the memory will co ntinue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to ?1?. all previous data in the selected blocks is lost.
m29f010b command interface 17/35 4.9 erase suspend command the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend wi thin 15s of the er ase suspend command being issued. once the program/erase contro ller has stopped the memory will be set to read mode and the erase will be suspended. if the erase su spend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the er ase is suspended imme diately and will start immediately when the erase resu me command is issued. it will not be possible to select any further blocks for erasure after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. reading from blocks that are being erased will output the st atus register. it is also possible to enter the auto select mode: the memory will behave as in the auto select mode on all blocks until a read/reset command returns the memory to erase suspend mode. 4.10 erase resume command the erase resume command must be used to restart the program/erase controller from erase suspend. an erase can be suspended and resumed more than once.
command interface m29f010b 18/35 table 4. commands (1) 1. all values in the table are in hexadecimal. x don?t care, pa program ad dress, pd program data, ba any address in the block. the command interface only uses address bits a0-a10 to verify the commands, the upper address bits are don?t care. command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset (2) 2. after a read/reset command, read the memory as normal until another command is issued. 1x f0 3555 aa2aa 55 x f0 auto select (3) 3. after an auto select command, read manufacture r id, device id or bl ock protection status. 3 555 aa 2aa 55 555 90 program (4) 4. after program, unlock bypass program, chip erase, and block erase commands read the status register until the program/erase controller completes and the memory returns to read mode. add additional blocks during block erase command with additi onal bus write operations until the timeout bit is set. 4 555 aa 2aa 55 555 a0 pa pd unlock bypass (5) 5. after the unlock bypass command issue unlock by pass program or unlock bypass reset commands. 3 555 aa 2aa 55 555 20 unlock bypass program (4) 2 x a0 pa pd unlock bypass reset (6) 6. after the unlock bypass reset command read the me mory as normal until another command is issued. 2x 90 x 00 chip erase (4) 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase (4) 6 + 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend (7) 7. after the erase suspend command read non-erasing memo ry blocks as normal, issue auto select and program commands on non-eras ing blocks as normal. 1x b0 erase resume (8) 8. after the erase resume command the suspended erase oper ation resumes, read the status register until the erase controller completes and the memory returns to read mode. 1x 30
m29f010b command interface 19/35 ) table 5. program erase times and program erase endurance cycles (1) 1. t a = 0 to 70c, ?40 to 85c. parameter min typ (2) 2. t a = 25c, v cc = 5v. typical after 100k w/e cycles (2) max unit chip erase (all bits in the memory set to ?0?) 0.6 0.6 sec chip erase 1.3 1.3 6 sec block erase (16 kbytes) 0.3 0.3 2 sec program 8 8 150 s chip program 1.2 1.2 4.5 sec program/erase cycles (per block) 100,000 cycles
status register m29f010b 20/35 5 status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase suspend when an address within a block being erased is accessed. the bits in the status register are summarized in table 6: status register bits . 5.1 data polling bit (dq7) the data polling bit can be used to identi fy whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bi t outputs the complement of the bit being programmed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the address just programmed output dq7, not its complement. during erase operations the data polling bit ou tputs ?0?, the compleme nt of the erased state of dq7. after successful completion of the erase operation the memory returns to read mode. in erase suspend mode the da ta polling bit will output a ?1? during a bus read operation within a block being erased. the data polling bit will change from a ?0? to a ?1? when the program/erase controller has suspended the erase operation. figure 4: data polling flowchart , gives an example of how to use the data polling bit. a valid address is the address being programmed or an address within the block being erased. 5.2 toggle bit (dq6) the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations at any addres s. after successful completion of the operation the memory returns to read mode. during erase suspend mo de the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop togglin g when the program/erase controller has suspended the erase operation. figure 5: data toggle flowchart , gives an example of how to use the data toggle bit.
m29f010b status register 21/35 5.3 error bit (dq5) the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to ?1? when a program, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set at ?0? back to ?1? and attempting to do so may or may not set dq5 at ?1?. in bo th cases, a successive bus read operation will show the bit is still ?0?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. 5.4 erase timer bit (dq3) the erase timer bit can be used to identify the start of program/erase controller operation during a block erase command. once the program/erase controller starts erasing the erase timer bit is set to ?1?. before the program/erase controller starts the erase timer bit is set to ?0? and additional blocks to be eras ed may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. 5.5 alternative toggle bit (dq2) the alternative toggle bit can be used to monitor the program/erase controller during erase operations. the alternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations from addresses within the blocks being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to addresses within blocks not be ing erased will output the me mory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the error. the alternative toggle bit changes from ?0? to ?1? to ?0 ?, etc. with successive bus read operations from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased correctly.
status register m29f010b 22/35 figure 4. data polling flowchart table 6. status register bits (1) 1. unspecified data bits should be ignored. operation address dq7 dq6 dq5 dq3 dq2 program any address dq7 toggle 0 ? ? program during erase suspend any address dq7 toggle 0 ? ? program error any address dq7 toggle 1 ? ? chip erase any address 0 toggle 0 1 toggle block erase before timeout erasing block 0 toggle 0 0 toggle non-erasing block 0 toggle 0 0 no toggle block erase erasing block 0 toggle 0 1 toggle non-erasing block 0 toggle 0 1 no toggle erase suspend erasing block 1 no toggle 0 ? toggle non-erasing block data read as normal erase error good block address 0 toggle 1 1 no toggle faulty block address 0 toggle 1 1 toggle read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no
m29f010b status register 23/35 figure 5. data toggle flowchart read dq6 start read dq6 twice fail pass ai01370b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
maximum rating m29f010b 24/35 6 maximum rating except for the rating "operating temperature range", stresses above those listed in table 7: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this spec ification is not implied. exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 7. absolute maximum ratings symbol parameter value unit t a ambient operating temperature (temperature range 1) 0 to 70 c ambient operating temperature (temperature range 6) ?40 to 85 c t bias temperature under bias ?50 to 125 c t stg storage temperature ?65 to 150 c v io (1) 1. minimum voltage may undershoot to ?2v during trans ition and for less than 20ns during transitions. input or output voltage ?0.6 to 6 v v cc supply voltage ?0.6 to 6 v v id identification volt age ?0.6 to 13.5 v
m29f010b dc and ac parameters 25/35 7 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 8: ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 6. ac testing input/output waveform table 8. ac measurement conditions parameter 45 70/90/120 ac test conditions high speed standard load capacitance (c l ) 30pf 100pf input rise and fall times 10ns 10ns input pulse voltages 0 to 3v 0.45 to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v ai01275b 3v high speed 0v 1.5v 2.4v standard 0.45v 2.0v 0.8v
dc and ac parameters m29f010b 26/35 figure 7. ac testing load circuit table 9. capacitance (1)(2) 1. t a = 25 c, f = 1 mhz. 2. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf ai03027 1.3v out c l = 30pf or 100pf c l includes jig capacitance 3.3k ? 1n914 device under test
m29f010b dc and ac parameters 27/35 table 10. dc characteristics (1) 1. t a = 0 to 70c, ?40 to 85c. symbol parameter test condition min typ (2) 2. t a = 25, v cc = 5v. max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 515ma i cc2 supply current (standby) ttl e = v ih 1ma i cc3 supply current (standby) cmos e = v cc 0.2v 30 100 a i cc4 (3) 3. sampled only, not 100% tested. supply current (program/erase) program/erase controller active 20 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 2 v cc +0.5 v v ol output low voltage i ol = 5.8ma 0.45 v v oh output high voltage ttl i oh = ?2.5ma 2.4 v output high voltage cmos i oh = ?100a v cc ?0.4 v v id identification voltage 11.5 12.5 v i id identification current a9 = v id 100 a v lko (3) program/erase lockout supply voltage 3.2 4.2 v
dc and ac parameters m29f010b 28/35 figure 8. read mode ac waveforms table 11. read ac characteristics (1) 1. ta = 0 to 70c, ?40 to 85c. symbol alt parameter test condition 45 70/90/120 unit t avav t rc address valid to next address valid e = v il , g = v il min 45 70 ns t avqv t acc address valid to output valid e = v il , g = v il max 45 70 ns t elqx (2) 2. sampled only, not 100% tested. t lz chip enable low to output transition g = v il min 0 0 ns t elqv t ce chip enable low to output valid g = v il max 45 70 ns t glqx (2) t olz output enable low to output transition e = v il min 0 0 ns t glqv t oe output enable low to output valid e = v il max 25 30 ns t ehqz (2) t hz chip enable high to output hi-z g = v il max 15 20 ns t ghqz (2) t df output enable high to output hi-z e = v il max 15 20 ns t ehqx , t ghqx , t axqx t oh chip enable, output enable or address transition to output transition min 0 0 ns ai0 2 tavav tavqv taxq x telqx tehqz tglqv tglqx tghqx valid -a16 q 0-dq7 telqv tehq x tghqz valid
m29f010b dc and ac parameters 29/35 figure 9. write ac waveforms, write enable controlled table 12. write ac characteristics, write enable controlled (1) 1. t a = 0 to 70 c, ?40 to 85 c. symbol alt parameter 45 70/90/120 unit t avav t wc address valid to next address valid min 45 70 ns t elwl t cs chip enable low to write enable low min 0 0 ns t wlwh t wp write enable low to write enable high min 40 45 ns t dvwh t ds input valid to write enable high min 25 30 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whwl t wph write enable high to write enable low min 20 20 ns t avwl t as address valid to write enable low min 0 0 ns t wlax t ah write enable low to address transition min 40 45 ns t ghwl output enable high to write enable low min 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 ns t vchel t vcs v cc high to chip enable low min 50 50 s ai02927 e g w a0-a16 dq0-dq7 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl
dc and ac parameters m29f010b 30/35 figure 10. write ac waveforms, chip enable controlled table 13. write ac characteristics, chip enable controlled (1) 1. t a = 0 to 70 c, ?40 to 85 c. symbol alt parameter 45 70/90/120 unit t avav t wc address valid to next address valid min 45 70 ns t wlel t ws write enable low to chip enable low min 0 0 ns t eleh t cp chip enable low to chip enable high min 40 45 ns t dveh t ds input valid to chip enable high min 25 30 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t ehel t cph chip enable high to chip enable low min 20 20 ns t avel t as address valid to chip enable low min 0 0 ns t elax t ah chip enable low to address transition min 40 45 ns t ghel output enable high chip enable low min 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 ns t vchwl t vcs v cc high to write enable low min 50 50 s ai02928 e g w a0-a16 dq0-dq7 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel
m29f010b package mechanical 31/35 8 package mechanical figure 11. plcc32 ? 32 lead plastic leaded chip carrier, package outline 1. drawing is not to scale. table 14. plcc32 ? 32 lead plastic leaded chip carrier, package mechanical data symbol millimeters inches typ min max typ min max a 3.17 3.56 0.125 0.140 a1 1.53 2.41 0.060 0.095 a2 0.38 ? 0.015 ? b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 cp 0.10 0.004 d 12.32 12.57 0.485 0.495 d1 11.35 11.51 0.447 0.453 d2 4.78 5.66 0.188 0.223 d3 7.62 ? ? 0.300 ? ? e 14.86 15.11 0.585 0.595 e1 13.89 14.05 0.547 0.553 e2 6.05 6.93 0.238 0.273 e3 10.16 ? ? 0.400 ? ? e1.27? ?0.050? ? f 0.00 0.13 0.000 0.005 n32 32 r 0.89 ? ? 0.035 ? ? plcc-a d e3 e1 e 1 n d1 d3 cp b e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 e2 d2 d2
package mechanical m29f010b 32/35 figure 12. tsop32 ? 32 lead plastic thin small outline, 8 x 20mm, package outline note: drawing is not to scale. table 15. tsop32 ? 32 lead plastic thin small outline, 8 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.25 0.0067 0.0098 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 7.90 8.10 0.3110 0.3189 e0.50? ?0.0197? ? l 0.50 0.70 0.0197 0.0276 0 5 0 5 n 32 32 cp 0.10 0.0039 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1
m29f010b part numbering 33/35 9 part numbering for a list of available options (speed, package, etc...) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 16. ordering information scheme (1) 1. the last two characters of t he ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are sh ipped from the factory with the me mory content bits erased to ?1?. example: m29 f010b 70 n 1 t device type m29 operating voltage f = v cc = 5v 10% device function 010b = 1 mbit (128kb x8), uniform block speed 45 = 45 ns 70 = 70 ns 90 = 90 ns 120 = 120ns package k = plcc32 n = tsop32: 8 x 20 mm temperature range 1 = 0 to 70c 6 = ?40 to 85c option blank = standard packing t = tape & reel packing e = ecopack package, standard packing f = ecopack package, tape & reel packing
revision history m29f010b 34/35 10 revision history table 17. revision history date revision revision details july 1999 -01 first issue 28-jul-2000 -02 new document template document type: from preliminary data to data sheet status register bit dq5 clarification data polling flowchart diagram change ( figure 4 ) data toggle flowchart diagram change ( figure 5 ) program/erase times specification change (table 5) i cc1 and i cc3 typ. specification added (table 10) 22-apr-2002 -03 plcc32 package mechanical data modified 19-sep-2005 4.0 pdip32 package removed. table 16: ordering information scheme : standard package added and ecopack version added for both standard package, and tape & reel packing. 06-nov-2006 5 converted document to new template; updated package mechanical data in section 8: package mechanical ; removed temperature range 3 (?40 to 125c) from entire document.
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